ARM11 Family Features:

Powerful ARMv6 instruction set architecture

ARM Thumb instruction set reduces memory bandwidth and size requirements by up to 35%

ARM Jazelle technology for efficient embedded Java execution

ARM DSP extensions

SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing

ARM TrustZone technology for on-chip security foundation (ARM1176JZ-S and ARM1176JZF-S cores)

Thumb-2 core technology for enhanced performance, energy efficiency and code density (ARM1156T2-S and ARM1156T2F-S cores)

Low power consumption:

0.6mW/MHz (0.13µm, 1.2V) including cache controllers

Energy saving power-down modes address static leakage currents in advanced processes

Intelligent Energy Manager (IEM) technology for dynamic power management (ARM1176JZ-S and ARM1176JZF-S cores)

High performance integer processor

8-stage integer pipeline delivers high clock frequency (9 stages for ARM1156T2(F)-S)

Separate load-store and arithmetic pipelines

Branch Prediction and Return Stack

High performance memory system design

Supports 4-64k cache sizes

Optional tightly coupled memories with DMA for multi-media applications

High-performance 64-bit memory system speeds data access for media processing and networking applications

ARMv6 memory system architecture accelerates OS context-switch

Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance

Optional Vector Floating Point coprocessor (ARM1136JF-S, ARM1176JZF-S and ARM1156T2F-S cores) for automotive/industrial controls and 3D graphics acceleration

All ARM11 cores are delivered as ARM- Synopsys Reference Methodology compliant deliverables which significantly reduce the time to generate a specific technology implementation of the core and to generate a complete set of industry standard views and models.

For a full list of public ARM11 processor licensees, click here

Related Links
White Paper - The ARMv6 Microarchitecture(PDF 199KB)
White Paper - ARM11 Core and PrimeXsys Platform(PDF 159KB)

Supporting Products by ARM Processor

The ARM11 family of processors is complemented by the range of ARM11 PrimeXsys Platforms and ETK11 which provide a foundation for efficient and rapid implementation of ARM11 core-based designs. ARM PrimeXsys Platforms provide a comprehensive set of peripherals, pre-configured with a flexible high-performance interconnect, and are readily extendable with customers’ own or third party IP.The CoreSight range of embedded debug products provides the ability to trace execution of the ARM11 processors in real-time and gives debug visibility of the entire ARM11 SoC.

A wide range of development tools is also available from ARM and third parties.

*ARM1176JZ-S and ARM1176JZF-S processors are also suitable for all application areas covered by ARM1136J-S, but with the added advantage of TrustZone technology where a trusted computing platform is required.

ARM11 MPCore Multiprocessor

The ARM11 MPCore synthesizable multiprocessor is based on the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to 2600 Dhrystone MIPS of performance.The ARM11 MPCore multiprocessor solution delivers greater performance at lower frequencies than comparable single processor solutions, bringing significant cost savings to system designers, while maintaining full compatibility with existing EDA tools and flows. The ARM11 MPCore processor also simplifies otherwise complex multiprocessor designs, reducing time-to-market and design costs.

Processors for Network Infrastructure, Consumer, and Automotive Infotainment in ARM Processor

The award-winning ARM1136J-S and ARM1136JF-S processors, feature the ARMv6 instruction set with media extensions, ARM Jazelle technology, ARM Thumb code compression, and optional floating point coprocessor. As with all ARM11 family processors, media processing extensions offer up to 1.9x acceleration of media-processing tasks such as MPEG4 encode, instruction and data cache sizes are configurable, and optional Tightly Coupled Memories can be added to accelerate interrupt handling and data-processing. These processors feature AMBA 2 AHB interfaces compatible with a wide range of system IP and peripherals.

High Performance Processors for Automotive, Data Storage, Imaging and Embedded Control in ARM Processor

The ARM1156T2-S and ARM1156T2F-S processors incorporate the latest ARM Thumb-2 technology for even higher code density and instruction set efficiency. Thumb-2 technology uses 31 percent less memory than pure 32-bit code to reduce system cost, while at the same time delivering up to 38 percent better performance than existing Thumb technology-based solutions. These processors also feature optional parity protection for caches and Tightly Coupled Memories (TCM), and non- maskable interrupts, making them ideal for embedded control applications where high reliability or high availability are paramount.
The ARM1156T2F-S processor includes an integrated floating point coprocessor - ideal for embedded control applications developed from mathematical models. Both processors feature an enhanced Memory Protection Unit (MPU) and offer an ideal upgrade path for embedded control applications currently using ARM946E-STM, ARM966E-STM or older 16-bit processors.
These processors feature AMBA 3 AXI specification interfaces, offering higher system bus bandwidth with fewer bus layers and rapid timing closure.

TrustZoneTM and IEM Enabled Applications Processors for Consumer and Wireless in ARM Proceressor

The ARM1176JZ-S and ARM1176JZF-S processors featuring ARM TrustZone technology, and ARM Jazelle® technology for efficient embedded Java execution, are designed for use as applications processors in consumer and wireless products. ARM TrustZone technology provides support within the CPU and platform architecture for building the trusted computing environments required to enable protection of critical system functions from downloaded applications, copyright protection of downloaded media, safe over-the-air system upgrades.
Both processors feature the ARMv6 instruction set architecture, with media processing extensions, ARM Jazelle technology, and ARM Thumb® for compact code. The ARM1176JZF-S processor also features an integrated floating point coprocessor, which makes it particularly suitable for embedded 3D-graphics applications. These are also the first processors to integrate support for ARM Intelligent Energy Manager (IEM) technology which can reduce processor energy consumption by up to 60% - making them ideal for cell-phone, PDA, hand-held game and other portable consumer devices.
These processors feature AXI interfaces compatible with the latest AMBATM 3 AXITM specification, and offering higher system bus bandwidth with fewer bus layers and rapid timing closure.

About ARM11 Family

ARM11 MPCore, ARM1136J(F)-S, ARM1156T2(F)-S and ARM1176JZ(F)-S

Based on the ARM11 microarchitecture, the ARM11 processor family comprises a range of high performance microprocessors, delivering up to 740 Dhrystone 2.1 MIPS in 0.13µ process technology. The family comprises four main product lines, the ARM1136J(F)-S processor, the ARM1156T2(F)-S processor and the ARM1176JZ(F)-STM processor, each optimized for the specific requirements of different market segments, and the ARM11 MPCoreTM multiprocessor.

Other Related Technologies

In addition to the above technologies, several other system technologies with their own architecture provisions are available from ARM.

• Debug and Trace

ARM's debug and trace tools enable system developers to quickly debug real-time software, and to trace instruction execution and associated program data at full core speed. The debug and trace offering includes host based tools along with components such as EmbeddedICE, Embedded Trace Macrocell (ETM™), and the latest CoreSight™ technology, which form part of a modern SoC.

• AMBA®

The AMBA on-chip interconnect is an established, open specification that serves as a framework for SoC designs and IP library development. The AMBA Advanced High-performance Bus (AHB) interface is supported by all many ARM cores and provides a high-performance, fully-synchronous backplane. Multi-layer AHB represents a significant technical advance that reduces latencies and increases the bandwidth available to multi-master systems. Fully compatible with the current AHB specification, Multi-layer AHBTM is supported on the ARM926EJ-S™ core and by all members of the ARM10™ core family.In 2003, ARM announced the launch of the latest AMBA specification, the AMBA 3 AXITM protocol which is targeted at high performance, high clock frequency systems designs and includes a number of features that make it very suitable for high speed, submicron interconnect.

• ARM Intelligent Energy Manager ARM

Intelligent Energy Manager (IEMTM) technology implements advanced algorithms to optimally balance processor workload and energy consumption, while maximizing system responsiveness to meet end-user performance expectations. The Intelligent Energy Manager technology works with the OS and applications running on the mobile phone to dynamically adjust the required CPU performance level through a standard programmer's model.

Thumb-2 Technology

ARM and Thumb code each execute in their own processor state. Thumb-2 core technology adds a mixed mode capability, defining a new set of 32-bit instructions that execute alongside traditional 16-bit instructions in Thumb state. This reduces, or can remove, the need for balancing ARM and Thumb code in a system, providing ‘ARM levels of performance’ with ‘Thumb code density’.Thumb-2 technology builds on the success of Thumb technology, adding to ARM’s strengths as the leading supplier of low power, high performance processors and systems, supply cost effective and timely solutions across a wide range of market segments.

ARM TrustZone

The ARM TrustZone extensions provide hardware support for two separate address spaces, such that code executing in the non-secure world cannot gain access to any address space marked as secure. A new monitor mode supports transition between the two worlds. The technology provides a secure environment for system features such as key management and/or authentication mechanisms enabled by an open OS. The protection provided by the technology is necessary for consumer privacy and extending a range of services, such as mobile banking and multimedia entertainment, to widespread consumer adoption and use.

Vector Floating Point (VFP)

Vector Floating Point (VFP) coprocessor support is an architecture option. The VFP architecture supports single and double precision floating point arithmetic, and is fully IEEE 754 compliant with suitable software library support. The VFP architecture also includes a fully deterministic ‘Run fast Mode’.Provision of a hardware floating point is essential for many applications, and can be used as part of a SoC design flow using technical computing tools (eg MatLab® and MATRIXx®) to directly model the system and derive the application code. The vector processing capability of the ARM VFP can be used to increase performance of imaging applications such as scaling, 2D and 3D transforms, font generation, and digital filters.ARM currently has VFP support for the ARM9™, ARM10™ and ARM11™ processor families: VFP9-S™ and VFP10™. Additional VFP options, VFPv3, were introduced with the ARMv7 architecture.

NEON Media Acceleration Technology

ARM NEON technology is an architecture option with the ARMv7A architecture and is designed to address the demands of next generation high-performance, media intense, low power mobile handheld devices. NEON technology is a 64/128-bit hybrid SIMD architecture, developed by ARM to accelerate the performance of multimedia and signal processing applications including video encode/decode, 3D graphics, speech processing, compressed audio decoding, image processing, telephony and sound synthesis.

About ARMv7

The ARMv7 architecture lies below the CortexTM family of processors and defines three distinct processor profiles: the A profile for sophisticated, virtual memory-based OS and user applications; the R profile for real-time systems; and the M profile optimized for microcontroller and low-cost applications.All ARMv7 architecture profiles implement Thumb® -2 technology which is built on the foundation of the ARM industry-leading Thumb code compression technology, while retaining complete code compatibility with existing ARM solutions. The ARMv7 architecture also includes the NEON™ technology extensions to increase DSP and media processing throughput by up to 400 percent, and offers improved floating point support to address the needs of next generation 3D graphics and games physics, as well as traditional embedded control applications.

About ARMv6

The ARMv6 architecture, announced in 2001, features improvements in many areas covering the memory system, improved exception handling and better support for multiprocessing environments. ARMv6 also includes media instructions to support Single Instruction Multiple Data(SIMD) software execution. The SIMD extensions are optimized for a broad range of software applications including video and audio codecs, where the extensions increase performance by up to four times. In addition Thumb-2 and TrustZone® technologies were introduced as variants of the ARMv6 architecture. The first implementation of the ARMv6 architecture was the ARM1136J(F)-STM processor announced in Spring 2002, followed by the ARM1156T2(F)-STM and the ARM1176JZ(F)-STM processors in 2003.

About ARMv5TEJ

In 2000, the ARMv5TEJ architecture added the Jazelle® technology extension to support Java acceleration technology, which is particularly suited to small memory footprint designs. Jazelle technology’s acceleration of Java bytecodes provides significantly higher performance than a software-only based Java Virtual Machine (JVM), accelerating Java execution by 8x and providing an 80% reduction in power consumption compared to a non Java-accelerated core. This functionality gives platform developers increased freedom to run Java code alongside established operating systems (OS) and applications on an ARM processor

about ARMv5TE

In 1999, the ARMv5TE architecture introduced improvements to the Thumb architecture, along with ARM ‘Enhanced’ DSP instruction set extensions to the ARM ISA.The Thumb changes added a few new instructions along with improvements to Thumb/ARM interworking, greatly improving compiler capabilities and the ability to mix and match ARM versus Thumb routines to balance code size and performance.The enhanced DSP instructions include support for saturated arithmetic, and provide up to 70% performance improvement for audio DSP applications. Many systems require the flexibility of a microcontroller combined with the data-processing capability of a DSP, historically forcing designers to compromise performance with cost, or adopt complex multi processor strategies. The ‘E’ instruction set extensions were designed to provide a DSP capability in a general purpose CPU, resulting in improved performance and flexibility.

About ARMv4T

The ARMv4T architecture added the 16-bit Thumb® instruction set which enabled compilers to generate more compact code (memory savings of up to 35% over the equivalent 32-bit code), while retaining all the benefits of a 32-bit system.

About ARMv4

The oldest version of the architecture supported today. All previous versions are now obsolete. Implementations include some members of the ARM7™ processor family and Intel StrongARM® processors. ARMv4 can be considered a 32-bit ISA operating in a 32-bit address space.

The ARM Instruction Set Architecture

The ARM architecture provides support for the 32-bit ARM and 16-bit Thumb® Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle™), security (TrustZone™), Intelligent Energy Manager (IEM), SIMD, and NEONTM technologies.

The ARM ISA is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development.