Powerful ARMv6 instruction set architecture
ARM Thumb instruction set reduces memory bandwidth and size requirements by up to 35%
ARM Jazelle technology for efficient embedded Java execution
ARM DSP extensions
SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing
ARM TrustZone technology for on-chip security foundation (ARM1176JZ-S and ARM1176JZF-S cores)
Thumb-2 core technology for enhanced performance, energy efficiency and code density (ARM1156T2-S and ARM1156T2F-S cores)
Low power consumption:
0.6mW/MHz (0.13µm, 1.2V) including cache controllers
Energy saving power-down modes address static leakage currents in advanced processes
Intelligent Energy Manager (IEM) technology for dynamic power management (ARM1176JZ-S and ARM1176JZF-S cores)
High performance integer processor
8-stage integer pipeline delivers high clock frequency (9 stages for ARM1156T2(F)-S)
Separate load-store and arithmetic pipelines
Branch Prediction and Return Stack
High performance memory system design
Supports 4-64k cache sizes
Optional tightly coupled memories with DMA for multi-media applications
High-performance 64-bit memory system speeds data access for media processing and networking applications
ARMv6 memory system architecture accelerates OS context-switch
Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance
Optional Vector Floating Point coprocessor (ARM1136JF-S, ARM1176JZF-S and ARM1156T2F-S cores) for automotive/industrial controls and 3D graphics acceleration
All ARM11 cores are delivered as ARM- Synopsys Reference Methodology compliant deliverables which significantly reduce the time to generate a specific technology implementation of the core and to generate a complete set of industry standard views and models.
For a full list of public ARM11 processor licensees, click here
White Paper - The ARMv6 Microarchitecture(PDF 199KB)
White Paper - ARM11 Core and PrimeXsys Platform(PDF 159KB)
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